1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
Along with the miniaturization of semiconductor devices, it is desired to also miniaturize contacts for electrically connecting the impurity-diffused layer of a semiconductor substrate with a wiring line or the like.
As a manufacturing method advantageous to miniaturization, there is known a method including:
forming a diffused layer on the principal surface of a semiconductor substrate between select gate electrodes formed thereon;
forming a first barrier film on the sidewalls of the select gate electrodes and on the diffused layer;
forming a first insulating layer on the first barrier film;
forming silicide layers on the select gate electrodes;
forming a second barrier film on the silicide layers and on the first insulating layer;
forming an opening having a first width in the second barrier film on the diffused layer;
forming a second insulating layer on the second barrier film;
forming a mask layer on the second insulating layer;
forming an opening having a second width larger than the first width in the mask layer on the opening;
forming the upper portion of a contact hole having a bottom as wide as the second width by carrying out etching using the mask layer as a mask;
forming in the second barrier film the lower portion of the contact hole having a first width W1 and being as deep as to penetrate through the first insulating layer and the first barrier film and reach the diffused layer by starting etching from the position of the opening; and
burying a conducting layer in the upper and lower portions of the contact hole, thereby forming a contact.
In addition, in order to reduce the resistance of bit line contacts of a NAND-type flash memory, there is known a method of forming a low-concentration impurity-diffused layer on the surface of a semiconductor substrate between select transistors, forming a high-concentration impurity-diffused layer in the center of this low-concentration impurity-diffused layer, creating a contact hole on the high-concentration impurity-diffused layer, and burying a Ti/TiN laminated barrier metal film and a tungsten (W) film in the contact hole, thereby forming a bit line contact.
When forming such a bit line contact using such a method as described above, there may arise a displacement in the position where an opening having a first width W1 is to be formed due to misalignment in lithography, thereby causing part of the bottom surface of the bit line contact to protrude out of the high-concentration impurity-diffused layer into the low-concentration impurity-diffused layer.
The above-described method thus has the problem that if such protrusion into the low-concentration impurity-diffused layer as described above occurs, Ti and the substrate (silicon) react with each other in the low-concentration impurity-diffused layer to form a Ti silicide when filling the contact hole with the Ti/TiN laminated barrier metal film and the W film, resulting in junction leakage, since the low-concentration impurity-diffused layer is designed to be shallower than the high-concentration impurity-diffused layer.
The method also has the problem that bit line leakage occurs since a depletion layer is formed on the surface of the low-concentration impurity-diffused layer in the vicinity of the select transistors due to the electric fields thereof and a Ti silicide is formed in this depletion layer.
These problems can be avoided by reducing the size of the contacts (contact holes) or by increasing the distance between the select gate electrodes. However, reducing the size of contacts is makes it difficult to ensure a sufficient lithographic margin when forming a resist pattern for contacts in lithography, thereby leading to a decrease in the yield. Furthermore, increasing the distance between the select gate electrodes involves an increase in the chip size, resulting in a decrease in the number of chips produced from a single wafer.